The present invention relates to a method for planarizing depressed areas, such as contact holes, during the fabrication of an integrated circuit.
One difficulty in the fabrication of integrated circuit structures is the relatively large area which must be taken up by contact holes and vias. This is because, if the walls of a contact hole are too steep, step coverage problems may result when metal is deposited, so that a good electrical connection to the contact level does not result. Particularly if integrated circuits are to be formed using a large number of levels, such as double-metal circuits, a contact hole may have to be etched through a large thickness of material, and therefore may require a large width in the prior art.
A related difficulty is the vertical excursion which the topography of multi-level integrated circuits may create. That is, since the thickness variations of successive layers are cumulative, substantial thickness variation may result in the uppermost level, particularly in a structure which has more than two layers of conductors, such as a double-metal structure.
However, structures having more than two layers of conductors are highly desirable in large random logic integrated circuits, since they facilitate the circuit designer's task and reduce the average length of a connection.
Thus, it is an object of the present invention to provide a method for forming metal or silicide contacts to the bottom of a hole with very steep walls.
It is a further object of the present invention to provide a method for forming contacts to the bottom of a contact hole with vertical walls.
It is a further object of the present invention to provide a method for planarizing depressed areas in an integrated circuit structure by filling them with conductive material.
It is a further object of the present invention to provide a method for depositing metal over exposed portions of silicon or metal, which is insensitive to the height of the area where metal is to be deposited within the integrated circuit structure.
U.S. patent application Ser. No. 189,495, filed Sept. 22, 1980 (TI-8478), now issued as U.S. Pat. No. 4,388,517, which is hereby incorporated by reference, discloses a method for selective deposition of metal according to the thermal conductivities of different areas.
Allowed U.S. patent application Ser. No. 384,355 now U.S. Pat. No. 4,448,636 (TI-9353), which was filed simultaneously with the present application and which is hereby incorporated by reference, teaches a method for selective deposition of thin films on areas exposed by a patterned resist layer.
U.S. patent application Ser. No. 384,354 now U.S. Pat. No. 4,465,716 (TI-9515), which was filed simultaneously with the present application and which is hereby incorporated by reference, teaches a method for selective deposition of composite materials, such as silicides or TiW, onto areas exposed by a patterned insulator.